In some applications, processors may have a large percentage of memory access operations which transfer small amounts of data. Such memory access operations may be commonly known as burst length access (e.g., burst length reads and/or burst length writes). Current research suggests that for small burst length access, multiple narrow independent data channels accessing the memory devices may provide better performance than a single data channel having a wide memory interface. Accordingly, existing systems having single, wide-channel memory interface could benefit by increasing the number of data channels while reducing each data channel's bit width.
However, upgrading an existing processing system having a single data channel memory interface to one having dual memory interface may present some design challenges. For example, conventional memory interfaces using dual channels may have more complex circuitry associated with the addressing and/or control channels. This can lead to more complex packaging and circuit board designs, thus increasing the number of interface pins, circuit traces, etc. Such effects can have an adverse impact on cost and increase design risk. Moreover, such redesigns prevent any type of backwards compatibility with existing components and/or other existing sub-systems.
Accordingly, there is a need for a memory architecture having a dual narrow-channel interface which can utilize the existing pins meant for a wide channel interface. The resulting memory architecture may be implemented without impacting system cost resulting from an increased pin count.